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1 : : /*
2 : : * linux/include/linux/mtd/nand.h
3 : : *
4 : : * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 : : * Steven J. Hill <sjhill@realitydiluted.com>
6 : : * Thomas Gleixner <tglx@linutronix.de>
7 : : *
8 : : * This program is free software; you can redistribute it and/or modify
9 : : * it under the terms of the GNU General Public License version 2 as
10 : : * published by the Free Software Foundation.
11 : : *
12 : : * Info:
13 : : * Contains standard defines and IDs for NAND flash devices
14 : : *
15 : : * Changelog:
16 : : * See git changelog.
17 : : */
18 : : #ifndef __LINUX_MTD_NAND_H
19 : : #define __LINUX_MTD_NAND_H
20 : :
21 : : #include <linux/wait.h>
22 : : #include <linux/spinlock.h>
23 : : #include <linux/mtd/mtd.h>
24 : : #include <linux/mtd/flashchip.h>
25 : : #include <linux/mtd/bbm.h>
26 : :
27 : : struct mtd_info;
28 : : struct nand_flash_dev;
29 : : /* Scan and identify a NAND device */
30 : : extern int nand_scan(struct mtd_info *mtd, int max_chips);
31 : : /*
32 : : * Separate phases of nand_scan(), allowing board driver to intervene
33 : : * and override command or ECC setup according to flash type.
34 : : */
35 : : extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
36 : : struct nand_flash_dev *table);
37 : : extern int nand_scan_tail(struct mtd_info *mtd);
38 : :
39 : : /* Free resources held by the NAND device */
40 : : extern void nand_release(struct mtd_info *mtd);
41 : :
42 : : /* Internal helper for board drivers which need to override command function */
43 : : extern void nand_wait_ready(struct mtd_info *mtd);
44 : :
45 : : /* locks all blocks present in the device */
46 : : extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
47 : :
48 : : /* unlocks specified locked blocks */
49 : : extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
50 : :
51 : : /* The maximum number of NAND chips in an array */
52 : : #define NAND_MAX_CHIPS 8
53 : :
54 : : /*
55 : : * This constant declares the max. oobsize / page, which
56 : : * is supported now. If you add a chip with bigger oobsize/page
57 : : * adjust this accordingly.
58 : : */
59 : : #define NAND_MAX_OOBSIZE 744
60 : : #define NAND_MAX_PAGESIZE 8192
61 : :
62 : : /*
63 : : * Constants for hardware specific CLE/ALE/NCE function
64 : : *
65 : : * These are bits which can be or'ed to set/clear multiple
66 : : * bits in one go.
67 : : */
68 : : /* Select the chip by setting nCE to low */
69 : : #define NAND_NCE 0x01
70 : : /* Select the command latch by setting CLE to high */
71 : : #define NAND_CLE 0x02
72 : : /* Select the address latch by setting ALE to high */
73 : : #define NAND_ALE 0x04
74 : :
75 : : #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
76 : : #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
77 : : #define NAND_CTRL_CHANGE 0x80
78 : :
79 : : /*
80 : : * Standard NAND flash commands
81 : : */
82 : : #define NAND_CMD_READ0 0
83 : : #define NAND_CMD_READ1 1
84 : : #define NAND_CMD_RNDOUT 5
85 : : #define NAND_CMD_PAGEPROG 0x10
86 : : #define NAND_CMD_READOOB 0x50
87 : : #define NAND_CMD_ERASE1 0x60
88 : : #define NAND_CMD_STATUS 0x70
89 : : #define NAND_CMD_SEQIN 0x80
90 : : #define NAND_CMD_RNDIN 0x85
91 : : #define NAND_CMD_READID 0x90
92 : : #define NAND_CMD_ERASE2 0xd0
93 : : #define NAND_CMD_PARAM 0xec
94 : : #define NAND_CMD_GET_FEATURES 0xee
95 : : #define NAND_CMD_SET_FEATURES 0xef
96 : : #define NAND_CMD_RESET 0xff
97 : :
98 : : #define NAND_CMD_LOCK 0x2a
99 : : #define NAND_CMD_UNLOCK1 0x23
100 : : #define NAND_CMD_UNLOCK2 0x24
101 : :
102 : : /* Extended commands for large page devices */
103 : : #define NAND_CMD_READSTART 0x30
104 : : #define NAND_CMD_RNDOUTSTART 0xE0
105 : : #define NAND_CMD_CACHEDPROG 0x15
106 : :
107 : : #define NAND_CMD_NONE -1
108 : :
109 : : /* Status bits */
110 : : #define NAND_STATUS_FAIL 0x01
111 : : #define NAND_STATUS_FAIL_N1 0x02
112 : : #define NAND_STATUS_TRUE_READY 0x20
113 : : #define NAND_STATUS_READY 0x40
114 : : #define NAND_STATUS_WP 0x80
115 : :
116 : : /*
117 : : * Constants for ECC_MODES
118 : : */
119 : : typedef enum {
120 : : NAND_ECC_NONE,
121 : : NAND_ECC_SOFT,
122 : : NAND_ECC_HW,
123 : : NAND_ECC_HW_SYNDROME,
124 : : NAND_ECC_HW_OOB_FIRST,
125 : : NAND_ECC_SOFT_BCH,
126 : : } nand_ecc_modes_t;
127 : :
128 : : /*
129 : : * Constants for Hardware ECC
130 : : */
131 : : /* Reset Hardware ECC for read */
132 : : #define NAND_ECC_READ 0
133 : : /* Reset Hardware ECC for write */
134 : : #define NAND_ECC_WRITE 1
135 : : /* Enable Hardware ECC before syndrome is read back from flash */
136 : : #define NAND_ECC_READSYN 2
137 : :
138 : : /* Bit mask for flags passed to do_nand_read_ecc */
139 : : #define NAND_GET_DEVICE 0x80
140 : :
141 : :
142 : : /*
143 : : * Option constants for bizarre disfunctionality and real
144 : : * features.
145 : : */
146 : : /* Buswidth is 16 bit */
147 : : #define NAND_BUSWIDTH_16 0x00000002
148 : : /* Chip has cache program function */
149 : : #define NAND_CACHEPRG 0x00000008
150 : : /*
151 : : * Chip requires ready check on read (for auto-incremented sequential read).
152 : : * True only for small page devices; large page devices do not support
153 : : * autoincrement.
154 : : */
155 : : #define NAND_NEED_READRDY 0x00000100
156 : :
157 : : /* Chip does not allow subpage writes */
158 : : #define NAND_NO_SUBPAGE_WRITE 0x00000200
159 : :
160 : : /* Device is one of 'new' xD cards that expose fake nand command set */
161 : : #define NAND_BROKEN_XD 0x00000400
162 : :
163 : : /* Device behaves just like nand, but is readonly */
164 : : #define NAND_ROM 0x00000800
165 : :
166 : : /* Device supports subpage reads */
167 : : #define NAND_SUBPAGE_READ 0x00001000
168 : :
169 : : /* Options valid for Samsung large page devices */
170 : : #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
171 : :
172 : : /* Macros to identify the above */
173 : : #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
174 : : #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
175 : :
176 : : /* Non chip related options */
177 : : /* This option skips the bbt scan during initialization. */
178 : : #define NAND_SKIP_BBTSCAN 0x00010000
179 : : /*
180 : : * This option is defined if the board driver allocates its own buffers
181 : : * (e.g. because it needs them DMA-coherent).
182 : : */
183 : : #define NAND_OWN_BUFFERS 0x00020000
184 : : /* Chip may not exist, so silence any errors in scan */
185 : : #define NAND_SCAN_SILENT_NODEV 0x00040000
186 : : /*
187 : : * Autodetect nand buswidth with readid/onfi.
188 : : * This suppose the driver will configure the hardware in 8 bits mode
189 : : * when calling nand_scan_ident, and update its configuration
190 : : * before calling nand_scan_tail.
191 : : */
192 : : #define NAND_BUSWIDTH_AUTO 0x00080000
193 : :
194 : : /* Options set by nand scan */
195 : : /* Nand scan has allocated controller struct */
196 : : #define NAND_CONTROLLER_ALLOC 0x80000000
197 : :
198 : : /* Cell info constants */
199 : : #define NAND_CI_CHIPNR_MSK 0x03
200 : : #define NAND_CI_CELLTYPE_MSK 0x0C
201 : : #define NAND_CI_CELLTYPE_SHIFT 2
202 : :
203 : : /* Keep gcc happy */
204 : : struct nand_chip;
205 : :
206 : : /* ONFI features */
207 : : #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
208 : : #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
209 : :
210 : : /* ONFI timing mode, used in both asynchronous and synchronous mode */
211 : : #define ONFI_TIMING_MODE_0 (1 << 0)
212 : : #define ONFI_TIMING_MODE_1 (1 << 1)
213 : : #define ONFI_TIMING_MODE_2 (1 << 2)
214 : : #define ONFI_TIMING_MODE_3 (1 << 3)
215 : : #define ONFI_TIMING_MODE_4 (1 << 4)
216 : : #define ONFI_TIMING_MODE_5 (1 << 5)
217 : : #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
218 : :
219 : : /* ONFI feature address */
220 : : #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
221 : :
222 : : /* Vendor-specific feature address (Micron) */
223 : : #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
224 : :
225 : : /* ONFI subfeature parameters length */
226 : : #define ONFI_SUBFEATURE_PARAM_LEN 4
227 : :
228 : : /* ONFI optional commands SET/GET FEATURES supported? */
229 : : #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
230 : :
231 : : struct nand_onfi_params {
232 : : /* rev info and features block */
233 : : /* 'O' 'N' 'F' 'I' */
234 : : u8 sig[4];
235 : : __le16 revision;
236 : : __le16 features;
237 : : __le16 opt_cmd;
238 : : u8 reserved0[2];
239 : : __le16 ext_param_page_length; /* since ONFI 2.1 */
240 : : u8 num_of_param_pages; /* since ONFI 2.1 */
241 : : u8 reserved1[17];
242 : :
243 : : /* manufacturer information block */
244 : : char manufacturer[12];
245 : : char model[20];
246 : : u8 jedec_id;
247 : : __le16 date_code;
248 : : u8 reserved2[13];
249 : :
250 : : /* memory organization block */
251 : : __le32 byte_per_page;
252 : : __le16 spare_bytes_per_page;
253 : : __le32 data_bytes_per_ppage;
254 : : __le16 spare_bytes_per_ppage;
255 : : __le32 pages_per_block;
256 : : __le32 blocks_per_lun;
257 : : u8 lun_count;
258 : : u8 addr_cycles;
259 : : u8 bits_per_cell;
260 : : __le16 bb_per_lun;
261 : : __le16 block_endurance;
262 : : u8 guaranteed_good_blocks;
263 : : __le16 guaranteed_block_endurance;
264 : : u8 programs_per_page;
265 : : u8 ppage_attr;
266 : : u8 ecc_bits;
267 : : u8 interleaved_bits;
268 : : u8 interleaved_ops;
269 : : u8 reserved3[13];
270 : :
271 : : /* electrical parameter block */
272 : : u8 io_pin_capacitance_max;
273 : : __le16 async_timing_mode;
274 : : __le16 program_cache_timing_mode;
275 : : __le16 t_prog;
276 : : __le16 t_bers;
277 : : __le16 t_r;
278 : : __le16 t_ccs;
279 : : __le16 src_sync_timing_mode;
280 : : __le16 src_ssync_features;
281 : : __le16 clk_pin_capacitance_typ;
282 : : __le16 io_pin_capacitance_typ;
283 : : __le16 input_pin_capacitance_typ;
284 : : u8 input_pin_capacitance_max;
285 : : u8 driver_strength_support;
286 : : __le16 t_int_r;
287 : : __le16 t_ald;
288 : : u8 reserved4[7];
289 : :
290 : : /* vendor */
291 : : __le16 vendor_revision;
292 : : u8 vendor[88];
293 : :
294 : : __le16 crc;
295 : : } __packed;
296 : :
297 : : #define ONFI_CRC_BASE 0x4F4E
298 : :
299 : : /* Extended ECC information Block Definition (since ONFI 2.1) */
300 : : struct onfi_ext_ecc_info {
301 : : u8 ecc_bits;
302 : : u8 codeword_size;
303 : : __le16 bb_per_lun;
304 : : __le16 block_endurance;
305 : : u8 reserved[2];
306 : : } __packed;
307 : :
308 : : #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
309 : : #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
310 : : #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
311 : : struct onfi_ext_section {
312 : : u8 type;
313 : : u8 length;
314 : : } __packed;
315 : :
316 : : #define ONFI_EXT_SECTION_MAX 8
317 : :
318 : : /* Extended Parameter Page Definition (since ONFI 2.1) */
319 : : struct onfi_ext_param_page {
320 : : __le16 crc;
321 : : u8 sig[4]; /* 'E' 'P' 'P' 'S' */
322 : : u8 reserved0[10];
323 : : struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
324 : :
325 : : /*
326 : : * The actual size of the Extended Parameter Page is in
327 : : * @ext_param_page_length of nand_onfi_params{}.
328 : : * The following are the variable length sections.
329 : : * So we do not add any fields below. Please see the ONFI spec.
330 : : */
331 : : } __packed;
332 : :
333 : : struct nand_onfi_vendor_micron {
334 : : u8 two_plane_read;
335 : : u8 read_cache;
336 : : u8 read_unique_id;
337 : : u8 dq_imped;
338 : : u8 dq_imped_num_settings;
339 : : u8 dq_imped_feat_addr;
340 : : u8 rb_pulldown_strength;
341 : : u8 rb_pulldown_strength_feat_addr;
342 : : u8 rb_pulldown_strength_num_settings;
343 : : u8 otp_mode;
344 : : u8 otp_page_start;
345 : : u8 otp_data_prot_addr;
346 : : u8 otp_num_pages;
347 : : u8 otp_feat_addr;
348 : : u8 read_retry_options;
349 : : u8 reserved[72];
350 : : u8 param_revision;
351 : : } __packed;
352 : :
353 : : /**
354 : : * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
355 : : * @lock: protection lock
356 : : * @active: the mtd device which holds the controller currently
357 : : * @wq: wait queue to sleep on if a NAND operation is in
358 : : * progress used instead of the per chip wait queue
359 : : * when a hw controller is available.
360 : : */
361 : : struct nand_hw_control {
362 : : spinlock_t lock;
363 : : struct nand_chip *active;
364 : : wait_queue_head_t wq;
365 : : };
366 : :
367 : : /**
368 : : * struct nand_ecc_ctrl - Control structure for ECC
369 : : * @mode: ECC mode
370 : : * @steps: number of ECC steps per page
371 : : * @size: data bytes per ECC step
372 : : * @bytes: ECC bytes per step
373 : : * @strength: max number of correctible bits per ECC step
374 : : * @total: total number of ECC bytes per page
375 : : * @prepad: padding information for syndrome based ECC generators
376 : : * @postpad: padding information for syndrome based ECC generators
377 : : * @layout: ECC layout control struct pointer
378 : : * @priv: pointer to private ECC control data
379 : : * @hwctl: function to control hardware ECC generator. Must only
380 : : * be provided if an hardware ECC is available
381 : : * @calculate: function for ECC calculation or readback from ECC hardware
382 : : * @correct: function for ECC correction, matching to ECC generator (sw/hw)
383 : : * @read_page_raw: function to read a raw page without ECC
384 : : * @write_page_raw: function to write a raw page without ECC
385 : : * @read_page: function to read a page according to the ECC generator
386 : : * requirements; returns maximum number of bitflips corrected in
387 : : * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
388 : : * @read_subpage: function to read parts of the page covered by ECC;
389 : : * returns same as read_page()
390 : : * @write_subpage: function to write parts of the page covered by ECC.
391 : : * @write_page: function to write a page according to the ECC generator
392 : : * requirements.
393 : : * @write_oob_raw: function to write chip OOB data without ECC
394 : : * @read_oob_raw: function to read chip OOB data without ECC
395 : : * @read_oob: function to read chip OOB data
396 : : * @write_oob: function to write chip OOB data
397 : : */
398 : : struct nand_ecc_ctrl {
399 : : nand_ecc_modes_t mode;
400 : : int steps;
401 : : int size;
402 : : int bytes;
403 : : int total;
404 : : int strength;
405 : : int prepad;
406 : : int postpad;
407 : : struct nand_ecclayout *layout;
408 : : void *priv;
409 : : void (*hwctl)(struct mtd_info *mtd, int mode);
410 : : int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
411 : : uint8_t *ecc_code);
412 : : int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
413 : : uint8_t *calc_ecc);
414 : : int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
415 : : uint8_t *buf, int oob_required, int page);
416 : : int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
417 : : const uint8_t *buf, int oob_required);
418 : : int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
419 : : uint8_t *buf, int oob_required, int page);
420 : : int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
421 : : uint32_t offs, uint32_t len, uint8_t *buf);
422 : : int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
423 : : uint32_t offset, uint32_t data_len,
424 : : const uint8_t *data_buf, int oob_required);
425 : : int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
426 : : const uint8_t *buf, int oob_required);
427 : : int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
428 : : int page);
429 : : int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
430 : : int page);
431 : : int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
432 : : int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
433 : : int page);
434 : : };
435 : :
436 : : /**
437 : : * struct nand_buffers - buffer structure for read/write
438 : : * @ecccalc: buffer for calculated ECC
439 : : * @ecccode: buffer for ECC read from flash
440 : : * @databuf: buffer for data - dynamically sized
441 : : *
442 : : * Do not change the order of buffers. databuf and oobrbuf must be in
443 : : * consecutive order.
444 : : */
445 : : struct nand_buffers {
446 : : uint8_t ecccalc[NAND_MAX_OOBSIZE];
447 : : uint8_t ecccode[NAND_MAX_OOBSIZE];
448 : : uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
449 : : };
450 : :
451 : : /**
452 : : * struct nand_chip - NAND Private Flash Chip Data
453 : : * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
454 : : * flash device
455 : : * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
456 : : * flash device.
457 : : * @read_byte: [REPLACEABLE] read one byte from the chip
458 : : * @read_word: [REPLACEABLE] read one word from the chip
459 : : * @write_byte: [REPLACEABLE] write a single byte to the chip on the
460 : : * low 8 I/O lines
461 : : * @write_buf: [REPLACEABLE] write data from the buffer to the chip
462 : : * @read_buf: [REPLACEABLE] read data from the chip into the buffer
463 : : * @select_chip: [REPLACEABLE] select chip nr
464 : : * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
465 : : * @block_markbad: [REPLACEABLE] mark a block bad
466 : : * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
467 : : * ALE/CLE/nCE. Also used to write command and address
468 : : * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
469 : : * mtd->oobsize, mtd->writesize and so on.
470 : : * @id_data contains the 8 bytes values of NAND_CMD_READID.
471 : : * Return with the bus width.
472 : : * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
473 : : * device ready/busy line. If set to NULL no access to
474 : : * ready/busy is available and the ready/busy information
475 : : * is read from the chip status register.
476 : : * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
477 : : * commands to the chip.
478 : : * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
479 : : * ready.
480 : : * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
481 : : * setting the read-retry mode. Mostly needed for MLC NAND.
482 : : * @ecc: [BOARDSPECIFIC] ECC control structure
483 : : * @buffers: buffer structure for read/write
484 : : * @hwcontrol: platform-specific hardware control structure
485 : : * @erase_cmd: [INTERN] erase command write function, selectable due
486 : : * to AND support.
487 : : * @scan_bbt: [REPLACEABLE] function to scan bad block table
488 : : * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
489 : : * data from array to read regs (tR).
490 : : * @state: [INTERN] the current state of the NAND device
491 : : * @oob_poi: "poison value buffer," used for laying out OOB data
492 : : * before writing
493 : : * @page_shift: [INTERN] number of address bits in a page (column
494 : : * address bits).
495 : : * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
496 : : * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
497 : : * @chip_shift: [INTERN] number of address bits in one chip
498 : : * @options: [BOARDSPECIFIC] various chip options. They can partly
499 : : * be set to inform nand_scan about special functionality.
500 : : * See the defines for further explanation.
501 : : * @bbt_options: [INTERN] bad block specific options. All options used
502 : : * here must come from bbm.h. By default, these options
503 : : * will be copied to the appropriate nand_bbt_descr's.
504 : : * @badblockpos: [INTERN] position of the bad block marker in the oob
505 : : * area.
506 : : * @badblockbits: [INTERN] minimum number of set bits in a good block's
507 : : * bad block marker position; i.e., BBM == 11110111b is
508 : : * not bad when badblockbits == 7
509 : : * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
510 : : * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
511 : : * Minimum amount of bit errors per @ecc_step_ds guaranteed
512 : : * to be correctable. If unknown, set to zero.
513 : : * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
514 : : * also from the datasheet. It is the recommended ECC step
515 : : * size, if known; if unknown, set to zero.
516 : : * @numchips: [INTERN] number of physical chips
517 : : * @chipsize: [INTERN] the size of one chip for multichip arrays
518 : : * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
519 : : * @pagebuf: [INTERN] holds the pagenumber which is currently in
520 : : * data_buf.
521 : : * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
522 : : * currently in data_buf.
523 : : * @subpagesize: [INTERN] holds the subpagesize
524 : : * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
525 : : * non 0 if ONFI supported.
526 : : * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
527 : : * supported, 0 otherwise.
528 : : * @read_retries: [INTERN] the number of read retry modes supported
529 : : * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
530 : : * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
531 : : * @bbt: [INTERN] bad block table pointer
532 : : * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
533 : : * lookup.
534 : : * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
535 : : * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
536 : : * bad block scan.
537 : : * @controller: [REPLACEABLE] a pointer to a hardware controller
538 : : * structure which is shared among multiple independent
539 : : * devices.
540 : : * @priv: [OPTIONAL] pointer to private chip data
541 : : * @errstat: [OPTIONAL] hardware specific function to perform
542 : : * additional error status checks (determine if errors are
543 : : * correctable).
544 : : * @write_page: [REPLACEABLE] High-level page write function
545 : : */
546 : :
547 : : struct nand_chip {
548 : : void __iomem *IO_ADDR_R;
549 : : void __iomem *IO_ADDR_W;
550 : :
551 : : uint8_t (*read_byte)(struct mtd_info *mtd);
552 : : u16 (*read_word)(struct mtd_info *mtd);
553 : : void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
554 : : void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
555 : : void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
556 : : void (*select_chip)(struct mtd_info *mtd, int chip);
557 : : int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
558 : : int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
559 : : void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
560 : : int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
561 : : u8 *id_data);
562 : : int (*dev_ready)(struct mtd_info *mtd);
563 : : void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
564 : : int page_addr);
565 : : int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
566 : : void (*erase_cmd)(struct mtd_info *mtd, int page);
567 : : int (*scan_bbt)(struct mtd_info *mtd);
568 : : int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
569 : : int status, int page);
570 : : int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
571 : : uint32_t offset, int data_len, const uint8_t *buf,
572 : : int oob_required, int page, int cached, int raw);
573 : : int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
574 : : int feature_addr, uint8_t *subfeature_para);
575 : : int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
576 : : int feature_addr, uint8_t *subfeature_para);
577 : : int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
578 : :
579 : : int chip_delay;
580 : : unsigned int options;
581 : : unsigned int bbt_options;
582 : :
583 : : int page_shift;
584 : : int phys_erase_shift;
585 : : int bbt_erase_shift;
586 : : int chip_shift;
587 : : int numchips;
588 : : uint64_t chipsize;
589 : : int pagemask;
590 : : int pagebuf;
591 : : unsigned int pagebuf_bitflips;
592 : : int subpagesize;
593 : : uint8_t bits_per_cell;
594 : : uint16_t ecc_strength_ds;
595 : : uint16_t ecc_step_ds;
596 : : int badblockpos;
597 : : int badblockbits;
598 : :
599 : : int onfi_version;
600 : : struct nand_onfi_params onfi_params;
601 : :
602 : : int read_retries;
603 : :
604 : : flstate_t state;
605 : :
606 : : uint8_t *oob_poi;
607 : : struct nand_hw_control *controller;
608 : :
609 : : struct nand_ecc_ctrl ecc;
610 : : struct nand_buffers *buffers;
611 : : struct nand_hw_control hwcontrol;
612 : :
613 : : uint8_t *bbt;
614 : : struct nand_bbt_descr *bbt_td;
615 : : struct nand_bbt_descr *bbt_md;
616 : :
617 : : struct nand_bbt_descr *badblock_pattern;
618 : :
619 : : void *priv;
620 : : };
621 : :
622 : : /*
623 : : * NAND Flash Manufacturer ID Codes
624 : : */
625 : : #define NAND_MFR_TOSHIBA 0x98
626 : : #define NAND_MFR_SAMSUNG 0xec
627 : : #define NAND_MFR_FUJITSU 0x04
628 : : #define NAND_MFR_NATIONAL 0x8f
629 : : #define NAND_MFR_RENESAS 0x07
630 : : #define NAND_MFR_STMICRO 0x20
631 : : #define NAND_MFR_HYNIX 0xad
632 : : #define NAND_MFR_MICRON 0x2c
633 : : #define NAND_MFR_AMD 0x01
634 : : #define NAND_MFR_MACRONIX 0xc2
635 : : #define NAND_MFR_EON 0x92
636 : : #define NAND_MFR_SANDISK 0x45
637 : : #define NAND_MFR_INTEL 0x89
638 : :
639 : : /* The maximum expected count of bytes in the NAND ID sequence */
640 : : #define NAND_MAX_ID_LEN 8
641 : :
642 : : /*
643 : : * A helper for defining older NAND chips where the second ID byte fully
644 : : * defined the chip, including the geometry (chip size, eraseblock size, page
645 : : * size). All these chips have 512 bytes NAND page size.
646 : : */
647 : : #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
648 : : { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
649 : : .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
650 : :
651 : : /*
652 : : * A helper for defining newer chips which report their page size and
653 : : * eraseblock size via the extended ID bytes.
654 : : *
655 : : * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
656 : : * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
657 : : * device ID now only represented a particular total chip size (and voltage,
658 : : * buswidth), and the page size, eraseblock size, and OOB size could vary while
659 : : * using the same device ID.
660 : : */
661 : : #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
662 : : { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
663 : : .options = (opts) }
664 : :
665 : : #define NAND_ECC_INFO(_strength, _step) \
666 : : { .strength_ds = (_strength), .step_ds = (_step) }
667 : : #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
668 : : #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
669 : :
670 : : /**
671 : : * struct nand_flash_dev - NAND Flash Device ID Structure
672 : : * @name: a human-readable name of the NAND chip
673 : : * @dev_id: the device ID (the second byte of the full chip ID array)
674 : : * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
675 : : * memory address as @id[0])
676 : : * @dev_id: device ID part of the full chip ID array (refers the same memory
677 : : * address as @id[1])
678 : : * @id: full device ID array
679 : : * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
680 : : * well as the eraseblock size) is determined from the extended NAND
681 : : * chip ID array)
682 : : * @chipsize: total chip size in MiB
683 : : * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
684 : : * @options: stores various chip bit options
685 : : * @id_len: The valid length of the @id.
686 : : * @oobsize: OOB size
687 : : * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
688 : : * @ecc_strength_ds in nand_chip{}.
689 : : * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
690 : : * @ecc_step_ds in nand_chip{}, also from the datasheet.
691 : : * For example, the "4bit ECC for each 512Byte" can be set with
692 : : * NAND_ECC_INFO(4, 512).
693 : : */
694 : : struct nand_flash_dev {
695 : : char *name;
696 : : union {
697 : : struct {
698 : : uint8_t mfr_id;
699 : : uint8_t dev_id;
700 : : };
701 : : uint8_t id[NAND_MAX_ID_LEN];
702 : : };
703 : : unsigned int pagesize;
704 : : unsigned int chipsize;
705 : : unsigned int erasesize;
706 : : unsigned int options;
707 : : uint16_t id_len;
708 : : uint16_t oobsize;
709 : : struct {
710 : : uint16_t strength_ds;
711 : : uint16_t step_ds;
712 : : } ecc;
713 : : };
714 : :
715 : : /**
716 : : * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
717 : : * @name: Manufacturer name
718 : : * @id: manufacturer ID code of device.
719 : : */
720 : : struct nand_manufacturers {
721 : : int id;
722 : : char *name;
723 : : };
724 : :
725 : : extern struct nand_flash_dev nand_flash_ids[];
726 : : extern struct nand_manufacturers nand_manuf_ids[];
727 : :
728 : : extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
729 : : extern int nand_default_bbt(struct mtd_info *mtd);
730 : : extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
731 : : extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
732 : : extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
733 : : int allowbbt);
734 : : extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
735 : : size_t *retlen, uint8_t *buf);
736 : :
737 : : /**
738 : : * struct platform_nand_chip - chip level device structure
739 : : * @nr_chips: max. number of chips to scan for
740 : : * @chip_offset: chip number offset
741 : : * @nr_partitions: number of partitions pointed to by partitions (or zero)
742 : : * @partitions: mtd partition list
743 : : * @chip_delay: R/B delay value in us
744 : : * @options: Option flags, e.g. 16bit buswidth
745 : : * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
746 : : * @ecclayout: ECC layout info structure
747 : : * @part_probe_types: NULL-terminated array of probe types
748 : : */
749 : : struct platform_nand_chip {
750 : : int nr_chips;
751 : : int chip_offset;
752 : : int nr_partitions;
753 : : struct mtd_partition *partitions;
754 : : struct nand_ecclayout *ecclayout;
755 : : int chip_delay;
756 : : unsigned int options;
757 : : unsigned int bbt_options;
758 : : const char **part_probe_types;
759 : : };
760 : :
761 : : /* Keep gcc happy */
762 : : struct platform_device;
763 : :
764 : : /**
765 : : * struct platform_nand_ctrl - controller level device structure
766 : : * @probe: platform specific function to probe/setup hardware
767 : : * @remove: platform specific function to remove/teardown hardware
768 : : * @hwcontrol: platform specific hardware control structure
769 : : * @dev_ready: platform specific function to read ready/busy pin
770 : : * @select_chip: platform specific chip select function
771 : : * @cmd_ctrl: platform specific function for controlling
772 : : * ALE/CLE/nCE. Also used to write command and address
773 : : * @write_buf: platform specific function for write buffer
774 : : * @read_buf: platform specific function for read buffer
775 : : * @read_byte: platform specific function to read one byte from chip
776 : : * @priv: private data to transport driver specific settings
777 : : *
778 : : * All fields are optional and depend on the hardware driver requirements
779 : : */
780 : : struct platform_nand_ctrl {
781 : : int (*probe)(struct platform_device *pdev);
782 : : void (*remove)(struct platform_device *pdev);
783 : : void (*hwcontrol)(struct mtd_info *mtd, int cmd);
784 : : int (*dev_ready)(struct mtd_info *mtd);
785 : : void (*select_chip)(struct mtd_info *mtd, int chip);
786 : : void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
787 : : void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
788 : : void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
789 : : unsigned char (*read_byte)(struct mtd_info *mtd);
790 : : void *priv;
791 : : };
792 : :
793 : : /**
794 : : * struct platform_nand_data - container structure for platform-specific data
795 : : * @chip: chip level chip structure
796 : : * @ctrl: controller level device structure
797 : : */
798 : : struct platform_nand_data {
799 : : struct platform_nand_chip chip;
800 : : struct platform_nand_ctrl ctrl;
801 : : };
802 : :
803 : : /* Some helpers to access the data structures */
804 : : static inline
805 : : struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
806 : : {
807 : : struct nand_chip *chip = mtd->priv;
808 : :
809 : : return chip->priv;
810 : : }
811 : :
812 : : /* return the supported features. */
813 : : static inline int onfi_feature(struct nand_chip *chip)
814 : : {
815 [ # # ][ # # ]: 0 : return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
816 : : }
817 : :
818 : : /* return the supported asynchronous timing mode. */
819 : : static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
820 : : {
821 : : if (!chip->onfi_version)
822 : : return ONFI_TIMING_MODE_UNKNOWN;
823 : : return le16_to_cpu(chip->onfi_params.async_timing_mode);
824 : : }
825 : :
826 : : /* return the supported synchronous timing mode. */
827 : : static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
828 : : {
829 : : if (!chip->onfi_version)
830 : : return ONFI_TIMING_MODE_UNKNOWN;
831 : : return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
832 : : }
833 : :
834 : : /*
835 : : * Check if it is a SLC nand.
836 : : * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
837 : : * We do not distinguish the MLC and TLC now.
838 : : */
839 : : static inline bool nand_is_slc(struct nand_chip *chip)
840 : : {
841 : : return chip->bits_per_cell == 1;
842 : : }
843 : : #endif /* __LINUX_MTD_NAND_H */
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