Date: Thu, 27 Jun 1996 10:41:06 -0400
From: tomc@casco.East.Sun.COM (Tom Caron - Sun BOS Software)
Subject: Item #369: PCI Binding: available property for bus nodes

[ NOTE: Proposal text reformated to 80 char lines -- dmk ]

Title: "available" Property for PCI Bus Nodes

Author: Tom Caron

Date: 6/26/96

Ed/Tech: Technical

Synopsis: an "available" property should be provided to represent
	  unassigned address space

Doc & Version: PCI Bus Binding to IEEE Std 1275-1994 Standard for Boot Firmware
	Revision 1.75

Problem:

    There are some PCI devices, like PCI to PCMCIA bridges, that do not
    fully represent their PCI I/O and memory space requirements via their
    configuration header base address registers.  In the case of PCI to
    PCMCIA bridges, the base address registers represent the PCI I/O and
    memory space required by the bridge, but not by any PCMCIA cards that
    are inserted into the bridge's card slots.  PCMCIA cards may be
    "hot plugged", so PCMCIA cards may not even be present during boot.

    A property is needed to represent the unassigned PCI I/O and memory
    space on a PCI bus.  The operating system could use this property to
    provide a mechanism for allocating PCI I/O and memory space to device
    drivers for such devices.

Proposal:

    Add the following entry to the list of properties in section 3.1.2

	"available"

	   prop-name, describes the unassigned PCI I/O and memory space for the
	   PCI bus that the node represents.

	   prop-encoded-array: Arbitrary number of (phys-addr size) pairs.

	   phys-addr is (phys.lo phys.mid phys.hi), encoded as with
	   encode-phys.  size is a pair of integers, each encoded as
	   with encode-int.  The first integer denotes the most-significant
	   32 bits of the 64-bit region size, and the second integer denotes
	   the least significant 32 bits thereof.

	   This property is mandatory for PCI Bus Nodes, as defined by
	   Open Firmware.  The value consists of a sequence of
	   (phys-addr size) pairs.  Each such pair shall specify a
	   contiguous unassigned region of I/O or memory space (i.e. 
	   the ss field can be 01 denoting I/O space, 10 denoting
	   32-bit address memory space or 11 denoting 64-bit address
	   memory space and the n field should be 1 denoting the address
	   is not relocatable).

    Change the last paragraph in section 6 to read

	   After setting the Memory Base, Memory Limit, I/O Base and
	   I/O Limit registers, create a ranges property that represents
	   the Memory and I/O mappings that have been established and
	   create an available property that represents Memory and
	   I/O space defined by the Memory Base, Memory Limit, I/O
	   Base and I/O Limit registers that has not been assigned
	   to devices on the secondary bus.

	   Note: The PCI specification limits the smallest unit of space
	   defined by the I/O Base and I/O Limit registers to 1000h bytes
	   and the smallest unit of space defined by the Memory Base and
	   Memory Limit registers to 100000h.  An implementation may choose
	   to program these registers to include additional units of space
	   beyond the space assigned to devices on the secondary bus.
	   These additional units of space could be used by devices that
	   do not fully represent their address space requirements via their
	   base address registers, such as PCI to PCMCIA bridges.

[ P1275 Item #369 -- Received: Thu Jun 27 07:37:17 PDT 1996 ]